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? 2012-2015 microchip technology inc. ds20005142c-page 1 23a1024/23lc1024 device selection table features spi bus interface: - spi compatible - sdi (dual) and sqi (quad) compatible - 20 mhz clock rate for all modes low-power cmos technology: - read current: 3 ma at 5.5v, 20 mhz - standby current: 4 ? a at +85c unlimited read and write cycles zero write time 128k x 8-bit organization: - 32-byte page byte, page and sequential mode for reads and writes high reliability temperature ranges supported: rohs compliant 8 lead soic, tssop and pdip packages pin function table description the microchip technology inc. 23a1024/23lc1024 are 1 mbit serial sram devices. the memory is accessed via a simple serial peripheral interface (spi) compatible serial bus. the bus signals required are a clock input (sck), a data in line (si) and a data out line (so). access to the device is controlled through a chip select (cs ) input. additionally, sdi (serial dual interface) and sqi (serial quad interface) is supported if your application needs faster data rates. this device also supports unlimited reads and writes to the memory array. the 23a1024/23lc1024 is available in standard packages including 8-lead soic, pdip and advanced 8-lead tssop. package types (not to scale) part number v cc range temp. ranges dual i/o (sdi) quad i/o (sqi) max. clock frequency packages 23a1024 1.7-2.2v i, e yes yes 20 mhz (1) sn, st, p 23lc1024 2.5-5.5v i, e yes yes 20 mhz (1) sn, st, p note 1: 16 mhz for e-temp. - industrial (i): -40 ? cto +85 ? c - automotive (e): -40 ? c to +125 ? c name function cs chip select input pin so/sio1 serial output/sdi/sqi pin sio2 sqi pin v ss ground pin si/sio0 serial input/sdi/sqi pin sck serial clock pin hold /sio3 hold/sqi pin v cc power supply pin cs so/sio1 sio2 v ss v cc hold /sio3 sck si/sio0 12 3 4 87 6 5 soic/tssop/pdip 1mbit spi serial sram with sdi and sqi interface downloaded from: http:///
23a1024/23lc1024 ds20005142c-page 2 ? 2012-2015 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings (?) v cc .............................................................................................................................................................................6.5v all inputs and outputs w.r.t. v ss ........................................................................................................ -0.3v to v cc +0.3v storage temperature............................................................................................................ ...................-65c to +150c ambient temperature under bias................................................................................................. ...........-40c to +125c table 1-1: dc characteristics ? notice : stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating condit ions for an extended period of time may affect device reliability. dc characteristics industrial (i): t a = -40c to +85c automotive (e): t a = -40c to +125c param. no. sym. characteristic min. typ. (3) max. units test conditions d001 v cc supply voltage 1.7 2.2 v 23a1024 2.5 5.5 v 23lc1024 d002 v ih high-level input voltage 0.7v cc v cc + 0.3 v d003 v il low-level input voltage -0.3 0.2 v cc v 23a1024 0.1 v cc v 23lc1024 d004 v ol low-level output voltage 0 . 2vi ol = 1 ma d005 v oh high-level output voltage v cc - 0.5 v i oh = -400 ? a d006 i li input leakage current 1 ? a cs = v cc , v in = v ss or v cc d007 i lo output leakage current 1 ? a cs = v cc , v out = v ss or v cc d008 i cc read operating current 1 10 ma f clk = 20 mhz; so = o, 2.2v 31 0m a f clk = 20 mhz; so = o, 5.5v d009 i ccs standby current 1 4 ? a cs = v cc = 2.2v, inputs tied to v cc or v ss , i-temp 1 2 ? a cs = v cc = 2.2v, inputs tied to v cc or v ss , e-temp 41 0 ? a cs = v cc = 5.5v, inputs tied to v cc or v ss , i-temp 2 0 ? a cs = v cc = 5.5v, inputs tied to v cc or v ss , e-temp d010 c int input capacitance 7 pf v cc = 5.0v, f = 1 mhz, t a =25c ( note 1 ) d011 v dr ram data retention voltage 1 . 0 v ( note 2 ) note 1: this parameter is periodically sampled and not 100% tested. 2: this is the limit to which v cc can be lowered without losing ram data. this parameter is periodically sampled and not 100% tested. 3: typical measurements taken at room temperature. downloaded from: http:///
? 2012-2015 microchip technology inc. ds20005142c-page 3 23a1024/23lc1024 table 1-3: ac test conditions table 1-2: ac characteristics ac characteristics industrial (i): t a = -40c to +85c automotive (e): t a = -40c to +125c param. no. sym. characteristic min. max. units test conditions 1f clk clock frequency 20 mhz i-temp 16 mhz e-temp 2 t css cs setup time 25 ns i-temp 32 ns e-temp 3 t csh cs hold time 50 ns 4 t csd cs disable time 25 ns i-temp 32 ns e-temp 5t su data setup time 10 ns 6t hd data hold time 10 ns 7t r clk rise time 20 ns ( note 1 ) 8t f clk fall time 20 ns ( note 1 ) 9t hi clock high time 25 ns i-temp 32 ns e-temp 10 t lo clock low time 25 ns i-temp 32 ns e-temp 11 t cld clock delay time 25 ns i-temp 32 ns e-temp 12 t v output valid from clock low 25 ns i-temp 32 ns e-temp 13 t ho output hold time 0 ns ( note 1 ) 14 t dis output disable time 20 ns 15 t hs hold setup time 10 ns 16 t hh hold hold time 10 ns 17 t hz hold low to output high-z 10 ns 18 t hv hold high to output valid 50 ns note 1: this parameter is periodically sampled and not 100% tested. ac waveform input pulse level 0.1 v cc to 0.9 v cc input rise/fall time 5 ns c l = 30 pf timing measurement reference level input 0.5 v cc output 0.5 v cc downloaded from: http:///
23a1024/23lc1024 ds20005142c-page 4 ? 2012-2015 microchip technology inc. figure 1-1: hold timing figure 1-2: serial input timing (spi mode) figure 1-3: serial output timing (spi mode) cs sck so si hold 16 15 15 16 18 17 dont care 5 high-impedance n + 2 n + 1 n n - 1 n n + 2 n + 1 n n n - 1 cs sck si so 6 5 8 7 11 3 lsb in msb in high-impedance 2 4 cs sck so 10 9 12 msb out lsb out 3 14 dont care si 13 downloaded from: http:///
? 2012-2015 microchip technology inc. ds20005142c-page 5 23a1024/23lc1024 2.0 functional description 2.1 principles of operation the 23a1024/23lc1024 is an 1 mbit serial sram designed to interface directly with the serial peripheral interface (spi) port of many of todays popular microcontroller families, including microchips pic ? microcontrollers. it may also interface with microcontrollers that do not have a built-in spi port by using discrete i/o lines programmed properly in firmware to match the spi protocol. in addition, the 23a1024/23lc1024 is capable of operation in sdi and sqi modes. in sdi mode, the si and so data lines are bidirectional, allowing the transfer of two bits per clock pulse. in sqi mode, two additional data lines enable the transfer of four bits per clock pulse. the 23a1024/23lc1024 contains an 8-bit instruction register. the device is accessed via the si pin, with data being clocked in on the rising edge of sck. the cs pin must be low for the entire operation. table 2-1 contains a list of the possible instruction bytes and format for device operation. all instructions, addresses and data are transferred msb first, lsb last. 2.2 modes of operation the 23x1024 has three modes of operation that are selected by setting bits 7 and 6 in the mode register. the modes of operation are byte, page and burst. byte operation C is selected when bits 7 and 6 in the mode register are set to 00 . in this mode, the read/write operations are limited to only one byte. the command followed by the 24-bit address is clocked into the device and the data to/from the device is transferred on the next eight clocks ( figure 2-1 , figure 2-2 ). page operation C is selected when bits 7 and 6 in the mode register are set to 10 . the 23x1024 has 4096 pages of 32 bytes. in this mode, the read and write operations are limited to within the addressed page (the address is automatically incremented internally). if the data being read or written reaches the page boundary, then the internal address counter will increment to the start of the page ( figure 2-3 , figure 2-4 ). sequential operation C is selected when bits 7 and 6 in the mode register are set to 01 . sequential operation allows the entire array to be written to and read from. the internal address counter is automatically incremented and page boundaries are ignored. when the internal address counter reaches the end of the array, the address counter will roll over to 0x00000 ( figure 2-5 , figure 2-6 ). 2.3 read sequence the device is selected by pulling cs low. the 8-bit read instruction is transmitted to the 23a1024/23lc1024 followed by the 24-bit address, with the first seven msbs of the address being dont care bits. after the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the so pin. if operating in sequential mode, the data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. the internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. when the highest address is reached (1ffffh), the address counter rolls over to address 00000h, allowing the read cycle to be continued indefinitely. the read operation is terminated by raising the cs pin. 2.4 write sequence prior to any attempt to write data to the 23a1024/23lc1024, the device must be selected by bringing cs low. once the device is selected, the write command can be started by issuing a write instruction, followed by the 24-bit address, with the first seven msbs of the address being dont care bits, and then the data to be written. a write is terminated by the cs being brought high. if operating in page mode, after the initial data byte is shifted in, additional bytes can be shifted into the device. the address pointer is automatically incremented. this operation can continue for the entire page (32 bytes) before data will start to be overwritten. if operating in sequential mode, after the initial data byte is shifted in, additional bytes can be clocked into the device. the internal address pointer is automatically incremented. when the address pointer reaches the highest address (1ffffh), the address counter rolls over to (00000h). this allows the operation to continue indefinitely, however, previous data will be overwritten. downloaded from: http:///
23a1024/23lc1024 ds20005142c-page 6 ? 2012-2015 microchip technology inc. figure 2-1: byte read sequence (spi mode) figure 2-2: byte write sequence (spi mode) table 2-1: instruction set instruction name instruction format hex code description read 0000 0011 0x03 read data from memory array beginning at selected address write 0000 0010 0x02 write data to memory array beginning at selected address edio 0011 1011 0x3b enter dual i/o access (enter sdi bus mode) eqio 0011 1000 0x38 enter quad i/o access (enter sqi bus mode) rstio 1111 1111 0xff reset dual and quad i/o access (revert to spi bus mode) rdmr 0000 0101 0x05 read mode register wrmr 0000 0001 0x01 write mode register so si sck cs 0 234567891011 29303132333435363738 39 1 01 0 0 0 0 01 23 22 21 20 210 76543210 instruction 24-bit address data out high-impedance so si cs 9 1011 29303132333435363738 39 00 0 0 0 0 01 23 22 21 20 210 76543210 instruction 24-bit address data byte high-impedance sck 0 234567 1 8 downloaded from: http:///
? 2012-2015 microchip technology inc. ds20005142c-page 7 23a1024/23lc1024 figure 2-3: page read sequence (spi mode) figure 2-4: page write sequence (spi mode) 76543210 page x, word y si cs 9 1011 29303132333435363738 39 23 22 21 20 210 24-bit address sck 0 234567 1 8 so cs 76543210 page x, word 0 sck 40 42 43 44 45 46 47 41 76543210 page x, word 31 76543210 page x, word y+1 page x, word y so high-impedance si 01 0 0 0 0 01 instruction si cs 9 1011 29303132333435363738 39 23 22 21 20 210 76543210 24-bit address sck 0 234567 18 cs si 76543210 page x, word 0 76543210 page x, word 31 76543210 page x, word y+1 page x, word y page x, word y sck 40 42 43 44 45 46 47 41 00 0 0 0 0 01 instruction so high-impedance so high-impedance downloaded from: http:///
23a1024/23lc1024 ds20005142c-page 8 ? 2012-2015 microchip technology inc. figure 2-5: sequential re ad sequence (spi mode) si cs 9 1011 29303132333435363738 39 23 22 21 20 210 76543210 instruction 24-bit address page x, word y sck 0 234567 18 so cs 76543210 page x+1, word 1 sck 76543210 page x+1, word 0 76543210 page x, word 31 so cs 76543210 page x+n, word 31 sck 76543210 page x+n, word 1 76543210 page x+1, word 31 so si si 01 0 0 0 0 01 downloaded from: http:///
? 2012-2015 microchip technology inc. ds20005142c-page 9 23a1024/23lc1024 figure 2-6: sequential write sequence (spi mode) si cs 9 1011 29303132333435363738 39 00 0 0 0 0 01 23 22 21 20 210 76543210 instruction 24-bit address data byte 1 sck 0 234567 18 si cs 49 50 51 54 55 76543210 data byte n sck 40 42 43 44 45 46 47 41 48 76543210 data byte 3 76543210 data byte 2 52 53 so high-impedance so high-impedance downloaded from: http:///
23a1024/23lc1024 ds20005142c-page 10 ? 2012-2015 microchip technology inc. 2.5 read mode register instruction ( rdmr ) the read mode register instruction ( rdmr ) provides access to the mode register. the mode register may be read at any time. the mode register is formatted as follows: table 2-2: mode register the mode bits indicate the operating mode of the sram. the possible modes of operation are: 0 0 = byte mode 1 0 = page mode 0 1 = sequential mode (default operation) 1 1 = reserved bits 0 through 5 are reserved and should always be set to 0 . see figure 2-7 for the rdmr timing sequence. figure 2-7: read mode regi ster timing sequence ( rdmr ) 76543210 w/r w/r C C C C C C mode mode 00000 0 w/r = writable/readable so si cs 91011 12131415 11 0 0 0 0 00 7654 2 10 instruction data from mode register high-impedance sck 0 234567 1 8 3 downloaded from: http:///
? 2012-2015 microchip technology inc. ds20005142c-page 11 23a1024/23lc1024 2.6 write mode register instruction ( wrmr ) the write mode register instruction ( wrmr ) allows the user to write to the bits in the mode register as shown in table 2-2 . this allows for setting of the device operating mode. several of the bits in the mode register must be cleared to 0 . see figure 2-8 for the wrmr timing sequence. figure 2-8: write mode regi ster timing sequence ( wrmr ) 2.7 power-on state the 23a1024/23lc1024 powers on in the following state: the device is in low-power standby mode (cs = 1 ) a high-to-low-level transition on cs is required to enter active state so si cs 91011 12131415 01 0 0 0 0 00 7654 210 instruction data to mode register high-impedance sck 0 234567 18 3 downloaded from: http:///
23a1024/23lc1024 ds20005142c-page 12 ? 2012-2015 microchip technology inc. 3.0 pin descriptions the descriptions of the pins are listed in tab l e 3 - 1 . table 3-1: pin function table figure 3-1: spi, sdi and sqi pin configurations 3.1 chip select (cs ) a low level on this pin selects the device. a high level deselects the device and forces it into standby mode. when the device is deselected, so goes to the high-impedance state, allowing multiple parts to share the same spi bus. after power-up, a low level on cs is required, prior to any sequence being initiated. 3.2 serial output, serial i/o (so/sio1) the so/sio1 pin is used to transfer data out of the 23a1024/23lc1024 when the spi bus is being used. when in sdi or sqi bus modes, the so/sio1 pin is a bidirectional i/o pin. data is shifted out on this pin after the falling edge of the serial clock, and it is latched in on the rising edge of the serial clock. 3.3 serial i/o 2 (sio2) the sio2 pin is a bidirectional i/o pin used only in sqi mode. if not using sqi bus mode, this pin should not be left floating. deciding to pull the sio2 pin high would allow successful recovery of the bus from sqi bus mode in case an accidental eqio command has been registered. 3.4 serial input, serial i/o 0 (si/sio0) the si pin is used to transfer data into the device when the spi bus is being used. when in sdi or sqi bus modes, the si/sio0 pin is a bidirectional i/o pin. 3.5 serial clock (sck) the sck is used to synchronize the communication between a master and the 23a1024/23lc1024. instructions, addresses or data present on the si pin are latched on the rising edge of the clock input, while data on the so pin is updated after the falling edge of the clock input. 3.6 hold, serial i/o 3 (hold /sio3) when the device is in sqi bus mode, pin hold/sio3 is a bidirectional i/o pin. when in spi or sdi bus modes, the pin has the hold function. the hold pin is used to suspend transmission to the 23a1024/23lc1024 while in the middle of a serial sequence without having to avoid retransmitting the entire sequence over again. it must be held high any time this function is not being used. once the device is soic/pdip/tssop symbol description 1c s chip select input 2 so/sio1 serial output (spi)/serial i/o 1 (sdi)/serial i/o 1 (sqi) 3 sio2 serial i/o 2 (sqi) 4v ss ground 5 si/sio0 serial input (spi)/serial i/o 0 (sdi)/serial i/o 0 (sqi) 6 sck serial clock input 7h old /sio3 hold/serial i/o 3 8v cc power supply cs sio1 nu vss v cc hold sck sio0 12 3 4 87 6 5 sdi mode: cs sio1 sio2 vss v cc sio3 sck sio0 12 3 4 87 6 5 sqi mode: cs so nu vss v cc hold scksi 12 3 4 87 6 5 spi mode: note: pin 3 is not used in spi and sdi modes, and should not be left floating (s ee section 3.3 ?serial i/o (sio2)? ). downloaded from: http:///
? 2012-2015 microchip technology inc. ds20005142c-page 13 23a1024/23lc1024 selected and a serial sequence is underway, the hold pin may be pulled low to pause further serial communication without resetting the serial sequence. the hold pin should be brought low while sck is low, otherwise the hold function will not be invoked until the next sck high-to-low transition. the 23a1024/23lc1024 must remain selected during this sequence. the si and sck levels are dont cares during the time the device is paused and any transitions on these pins will be ignored. to resume serial communication, hold should be brought high while the sck pin is low, otherwise serial communication will not be resumed until the next sck high-to-low transition. the so line will tri-state immediately upon a high-to low transition of the hold pin, and will begin outputting again immediately upon a subsequent low-to-high transition of the hold pin, independent of the state of sck. hold functionality is not available when operating in sqi bus mode. downloaded from: http:///
23a1024/23lc1024 ds20005142c-page 14 ? 2012-2015 microchip technology inc. 4.0 dual and quad serial mode the 23a1024/23lc1024 also supports sdi (serial dual) and sqi (serial quad) mode of operation when used with compatible master devices. as a convention for sdi mode of operation, two bits are entered per clock using the sio0 and sio1 pins. bits are clocked msb first. for sqi mode of operation, four bits of data are entered per clock, or one nibble per clock. the nibbles are clocked msb first. 4.1 dual interface mode the 23a1024/23lc1024 supports serial dual input (sdi) mode of operation. to enter sdi mode the edio command must be clocked in ( figure 4-1 ). it should be noted that if the mcu resets before the sram, the user will need to determine the serial mode of operation of the sram and reset it accordingly. byte read and write sequence in sdi mode is shown in figure 4-2 and figure 4-3 . figure 4-1: enter sdi mode (edio) from spi mode sck 0 234567 1 si high-impedance so cs 00 0111 1 1 downloaded from: http:///
? 2012-2015 microchip technology inc. ds20005142c-page 15 23a1024/23lc1024 figure 4-2: byte read mode sdi figure 4-3: byte write mode sdi note 1: page and sequential mode are similar in that additional bytes can be clocked out before cs is brought high. 2: the first byte read after the address will be a dummy byte. cs 9 1011 121314151617181920 0 234567 18 1 0 0 14 12 10 8 642 22 20 18 16 0 0 0 15 13 11 9 753 23 21 19 17 1 24-bit address instruction dummy byte 21 22 23 642 0 753 1 data out sck sio0 sio1 0 1 0 note: page and sequential mode are similar in that additional bytes can be clocked in before cs is brought high. cs sck sio0 sio1 9 10111213141516171819 0 234567 1 8 22 20 18 16 14 12 10 8 6 4 20 6 4 0 2 0 0 0 0 23 21 19 17 15 13 11 9 7 5 31 7 5 1 3 0 0 0 1 instruction 24-bit address data in downloaded from: http:///
23a1024/23lc1024 ds20005142c-page 16 ? 2012-2015 microchip technology inc. 4.2 quad interface mode in addition to the serial dual interface (sdi) mode of operation serial quad interface (sqi) is also supported. in this mode the hold functionality is not available. to enter sqi mode the eqio command must be clocked in ( figure 4-4 ). figure 4-4: enter sqi mode (eqio) from spi mode figure 4-5: byte read mode sqi sck 0 234567 1 si high-impedance so cs 00 0111 0 0 note 1: page and sequential mode is similar in that additional bytes can be clocked out before cs is brought high. 2: the first byte read after the address will be a dummy byte. cs sck 0 234567 1 8 9 1 0 40 20 16 12 8 sio0 1 0 51 21 17 13 9 0 0 62 22 18 14 10 0 0 73 23 19 15 11 sio1 sio2 sio3 instruction 24-bit address dummy byte 10 11 4 0 5 1 6 2 7 3 data out downloaded from: http:///
? 2012-2015 microchip technology inc. ds20005142c-page 17 23a1024/23lc1024 figure 4-6: byte write mode sqi 4.3 exit sdi or sqi mode to exit from sdi mode, the rstio command must be issued. the command must be entered in the current device configuration, either sdi or sqi, see figure 4-7 and figure 4-8 . figure 4-7: reset sdi mode (rstio) ? from sdi mode cs sck 0 234567 1 8 9 0 0 404 0 20 16 12 8 sio0 1 0 5151 21 17 13 9 0 0 6262 22 18 14 10 0 0 7373 23 19 15 11 sio1 sio2 sio3 instruction 24-bit address data in note: page and sequential mode are similar in that additional bytes can be clocked out before cs is brought high. sck 02 3 1 sio0 cs sio1 1 1 11 1 1 1 1 downloaded from: http:///
23a1024/23lc1024 ds20005142c-page 18 ? 2012-2015 microchip technology inc. figure 4-8: reset sdi/sqi mode (rstio) ? from sqi mode sck 0 1 sio0 sio1 sio2 sio3 11 11 1 1 1 1 cs downloaded from: http:///
? 2012-2015 microchip technology inc. ds20005142c-page 19 23a1024/23lc1024 5.0 packaging information 5.1 package marking information 8-lead soic (3.90 mm) xxxxyyww xxxxxxxt nnn example: sn 1328 23a1024i 1l7 legend: xx...x part number or part number code t temperature (i, e) y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec ? designator for matte tin (sn) note : for very small packages with no room for the pb-free jedec ? designator , the marking will only appear on the outer carton or reel label. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 3 e 8-lead tssop example: xxxt yyww nnn 3abi 1328 1l7 part number 1st line marking codes pdip soic tssop 23a1024 23a1024 23a1024t 3abt 23lc1024 23lc1024 23lcbt 3lbt note: t = temperature grade (i, e) t/xxxnnn xxxxxxxx yyww 8-lead pdip i/p 1l7 23a1024 1343 example: 3 e downloaded from: http:///
23a1024/23lc1024 ds20005142c-page 20 ? 2012-2015 microchip technology inc. n e1 note 1 d 12 3 a a1 a2 l b1 b e e eb c downloaded from: http:///
? 2012-2015 microchip technology inc. ds20005142c-page 21 23a1024/23lc1024 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
23a1024/23lc1024 ds20005142c-page 22 ? 2012-2015 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2012-2015 microchip technology inc. ds20005142c-page 23 23a1024/23lc1024 downloaded from: http:///
23a1024/23lc1024 ds20005142c-page 24 ? 2012-2015 microchip technology inc. d n e e1 note 1 12 b e c a a1 a2 l1 l downloaded from: http:///
? 2012-2015 microchip technology inc. ds20005142c-page 25 23a1024/23lc1024 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
23a1024/23lc1024 ds20005142c-page 26 ? 2012-2015 microchip technology inc. appendix a: revision history revision a (july 2012) initial release. revision b (november 2013) added e-temp specs. revision c (january 2015) updated features section. updated description section. updated section 2.0, functional description. updated table 2-1. updated section 3.0, pin descriptions. updated table 3-1. updated section 4.0, dual and quad serial mode. minor typographical corrections. downloaded from: http:///
? 2012-2015 microchip technology inc. ds20005142c-page 27 23a1024/23lc1024 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchips customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under support, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support downloaded from: http:///
23a1024/23lc1024 ds20005142c-page 28 ? 2012-2015 microchip technology inc. notes: downloaded from: http:///
? 2012-2015 microchip technology inc. ds20005142c-page 29 23a1024/23lc1024 product identification system to order or obtain information, e.g., on pr icing or delivery, refer to the factory or the listed sales office. not all possible ordering options are shown below. . part no. x /xx package tape & reel device device: 23a1024 = 23lc1024 = 1 mbit, 1.7 - 2.2v, spi serial sram 1 mbit, 2.5 - 5.5v, spi serial sram tape & reel: blank = t= standard packaging (tube) ta p e & r e e l temperature range: i=e= -40 ? c to +85 ? c -40 ? c to +125 ? c package: sn = st = p= plastic soic (3.90 mm body), 8-lead plastic tssop (4.4 mm body), 8-lead plastic pdip (300 mil body), 8-lead examples: a) 23a1024-i/st = 1 mbit, 1.7-2.2v serial sram, industrial temp., tssop package b) 23lc1024t-i/sn = 1 mbit, 2.5-5.5v serial sram, industrial temp., tape & reel, soic package c) 23lc1024-i/p = 1 mbit, 2.5-5.5v serial sram, industrial temp., pdip package d) 23a1024-e/st = 1 mbit, 1.7-2.2v serial sram, extended temp., tssop package e) 23lc1024t-e/sn = 1 mbit, 2.5-5.5v serial sram, extended temp., tape & reel, soic package f) 23lc1024-e/p = 1 mbit, 2.5-5.5v serial sram, extended temp., pdip package C x tem p range downloaded from: http:///
23a1024/23lc1024 ds20005142c-page 30 ? 2012-2015 microchip technology inc. notes: downloaded from: http:///
? 2012-2015 microchip technology inc. ds20005142c-page 31 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet logo, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademar ks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2012-2015, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-63276-967-1 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory an d analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:///
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